Field of the Invention
The present invention relates to video processing, and in particular to a transform and inverse transform method and a transform and inverse transform circuit implementing the method thereof compatible with various video codec standards.
Description of the Related Art
Video encoders/decoders are widely used in daily life. For example, video encoders/decoders can be used on DVDs, VCDs, satellite and terrestrial TV broadcasting systems, and the Internet. Generally, online video content is compressed by various encoders. In order to view the video contents correctly, the user has to install a related video decoder. The input video frames are usually divided into macroblocks for encoding, and the size of each macroblock is usually a 16×16 luminance block and corresponding chrominance blocks. Afterwards, motion compensation of the macroblocks is performed to predict the current frame based on the encoded frames. The statistical correlation of the spatial domain is reduced by using the macroblock transform or sub-band division. The output coefficients of the transform are then quantized, and the quantized coefficients after entropy encoding become a portion of the output bitstream. Then, a symbol can be obtained by encoding the quantized coefficients. Generally, entropy encoding is performed by using variable-length encoding. The decoding process is the reverse of the encoding process, wherein the step, which the original information cannot be restored, is quantization. Accordingly, the original information should be restored as much as possible, and the process is regarded as inverse quantization.
Currently, various video compression standards are used in video codec systems on the market, such as H.264, VP8, and Real Video standards. However, the number of logic gates of the video codec systems is very large, and only a specific video codec standard can be processed in current video codec systems, which lacks flexibility.
In view of the above, there is a demand for a video codec system capable of effectively utilizing the logic gate circuits to reduce the chip area and being flexibly compatible with various video codec standards.